Sean C. Griffin | BurstCube

BurstCube is a 6U (30 cm x 20 cm x 10 cm) CubeSat. The instrument comprises four CsI(Tl) scintillator crystals read out with arrays of silicon photomultipliers (SiPMs). BurstCube's primary sciecne goal is to detect and characterize the electromagnetic counterparts to gravitational waves, namely short gamma-ray bursts (sGRBs). In addition to being a member of the BurstCube science team, I am also part of the team that designed and built the instrument. My main task on BurstCube is to implement the FPGA interface between the instrument and the instrument flight software (iFSW) running on the flight computer.

The BurstCube flight computer is built around the SpaceMicro CubeSat Space Processor (CSP) which is a space-qualified board built around the Xilinx Zynq SoC platform. The Zynq is a combined dual-core ARM processor with configurable FPGA fabric. BurstCube has two FPGAs (one for the instrument and one for the spacecraft). The first handles data acquisition from the SiPMs and instrument control. The second (which is what I work on) is the Command and Data Handling (C&DH) FPGA, Tis FPGA interface must process data as it arrives from the instrument, binning it into different energy channels and integrating it in time to reduce the overall data volume being sent to ground.

In this example, I am testing the logic that handles defining energy bins for one of the BurstCube datastreams, and then reading them back to verify that they are correct. When the RAM write-enable goes high, some the RAM is loaded (near the yellow line). Then, at a later point (where the blue markers are) the RAM is read out and into an output register.

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